High-Throughput Irregular LDPC Decoder

Abstract— This paper presents a high-throughput area-efficient decoder design for the irregular Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipelined stages. Furthermore, min-sum and loosely coupled algorithms are employed to reduce chip area, and early termination technique is applied to adjust the iterations. A rate1/2 2304-bit irregular LDPC decoder for 802.16e standard is implemented using ASIC design in 90nm CMOS process. The decoder can achieve the maximum throughput of 2.2Gbps at 10 iterations. The operating frequency is 950MHz and the chip area is only about 2.9mm.